Flash memory devices store data in the form of charge in a flash cell. Flash cells can be arranged in arrays such as NAND flash arrays, NOR flash arrays and the like. The flash memory arrays are usually partitioned to erase blocks that may include multiple pages. A flash memory cell has a CMOS transistor with an additional floating metal gate between the substrate and the transistors gate. The charge is stored in the floating gate and is injected to the floating gate during an operation known as programming. The charge may be removed during an operation known as an erase operation.
As the charge in the floating gate may vary contiguously, it is possible to store more than just one bit per flash transistor by using several charge levels to symbolize different sequences of bits.
FIG. 1A demonstrates a voltage level distribution for a 3 bpc (bits per cell) flash memory cell. The voltage level distribution includes eight lobes 101-108. Each lobe represents a 3-bit value.
The voltage level distributions shown in FIG. 1 illustrate non-overlapping lobes, however this is only schematic, and in practical cases the lobes may overlap. The reason for overlapping may be intentional, for obtaining high programming speed, or due to the retention effect. For floating gate devices, an “old” page, may introduce greater overlap between lobes than a new page, since after many program/erase (P/E) cycles there is some deterioration of the cell which affects retention. After a long duration, every lobe may have a larger standard deviation and may have a different mean location. These effects are also known as retention.
The 3 bpc cell includes a most significant bit (MSB), a central significant bit (CSB) and a least significant bit (LSB). A physical page of flash memory device may store three logical pages. This physical page is programmed one logical page after the other.
The programming includes various types of programming such as MSB programming, CSB programming and LSB programming.
MSB programming may include programming some of the cells are programmed to a single lobe and some are left in the erase state. At the end of the programming process only two lobes exist, the erase and the MSB lobe.
The CSB programming may include splitting each of the erase lobe and the MSB lobe into two lobes by further programming pulses, depending on the original state of each cell and the corresponding CSB bit.
The LSB programming may include splitting each of the four lobes to create 8 lobes, overall.
The logical pages are read by applying various types of read operations such as an MSB read (in which an MSB threshold 114 is used), a CSB read (in which two CSB thresholds 112 and 116 are used) and an LSB read (in which four LSB thresholds 111, 113, 115 and 117 are used).
MSB threshold 114 is positioned between lobes 104 and 105. CSB threshold 113 is positioned between lobes 103 and 104. CSB threshold 116 is positioned between lobes 106 and 107. LSB threshold 111 is positioned between lobes 101 and 102. LSB threshold 113 is positioned between lobes 103 and 104. LSB threshold 115 is positioned between lobes 105 and 106. LSB threshold 117 is positioned between lobes 107 and 108.
FIG. 1B shows similar distributions for the case of 2 bpc devices. There are four spaced apart lobes—an erase lobe 121 and three other lobes 122-124.
The logical pages are read by applying various types of read operations such as MSB read (in which a MSB threshold 132 is used) and LSB read (in which two LSB thresholds 131 and 133 are used).
MSB threshold 132 is positioned between lobes 122 and 123. LSB threshold 131 is positioned between lobes 121 and 122. LSB threshold 133 is positioned between lobes 123 and 124.
As mentioned, the lobe distributions are not constant throughout the life of the flash cell and change with retention. With retention, the distribution becomes larger and shifts towards the erase level. The higher the distribution, the larger the shift. This effectively shrinks the effective working window. Both the shrinkage of the window and the fattening of the distributions contribute to the increase in the number of errors after performing a page read.
FIG. 1C illustrates these effects. The upper threshold voltage distribution includes eight spaced apart lobes 141-148 and represents a state of a flash memory page just after the flash memory page has been programmed. The lower threshold voltage distribution includes overlapping lobes 151-158 that are wider than lobes 141-148. These effects become significantly worse as the block P/E cycles increase and as the flash memory technology nodes shrink.
The implications of the retention effect is that using the same set of read-thresholds just following a programming operation and then following retention time may contribute to the number of read errors. In fact, it may be impossible to find a satisfactory set of such read-thresholds. It is therefore crucial to optimally adjust the threshold positions to minimize the number of errors.
Copy-Back Operation
In many cases, it is required to copy a certain section in the flash memory device to a different location in the flash memory device. Most flash memory devices implement a specific command known as copy-back. The copy-back command allows an external controller (that does not belong to the flash memory device) to instruct the flash memory device to internally read a certain page and immediately program the page data to another location in the flash memory device. The flash memory device is usually equipped with a limited functionality controller that can perform memory transfers from and to the flash memory arrays of the flash memory device.
The copy-back operation allows the external controller to perform memory copying in a very efficient manner without the need to stream the data to the external controller and back to the flash memory device
This is even more important when the copy-back command is activated on several flash memory devices simultaneously. In that case, without the copy-back command, the interface to the flash memory devices would become a bottle-neck.
However, a copy-back command does not perform error correction. Therefore, it may be that following a copy-back command, the copied data will contain errors. As long as the error correction code (ECC) can correct these errors this may be fine but it may turn out to be a problem in the following two scenarios:                a. The data is being copied from a location that had undergone cycling and retention. As the copy-back command usually uses a default set of thresholds, the copied data may contain errors beyond the capabilities of the ECC to correct them.        b. The data being copied already contains errors from previous copy-back commands. Thus, errors may accumulate until the codewords are no longer correctable.        